1. Technical Field
The present invention relates to a process of manufacturing a semiconductor device, and more particularly, to a high-density plasma chemical vapor deposition process for forming a material layer in gap regions in a semiconductor device.
2. Discussion of Related Art
As semiconductor devices become more highly integrated, gap regions have higher aspect ratios because of an area between adjacent interconnections has been reduced. In addition, as an aspect ratio increases for gap regions, the filling of the gap regions becomes more difficult. Generally, an interlayer-insulating layer is formed to fill gap regions using a low-pressure chemical vapor deposition (LPCVD) process. However, there are some limitations in using a LPCVD process in filling gap regions having a high aspect ratio. Therefore, a high-density plasma CVD process has been proposed because a high-density plasma CVD technique has improved gap-filling characteristics over the LPCVD and has been widely used in fabrication of the highly integrated semiconductor devices. Further, a high-density plasma CVD process fills a gap region having a high aspect ratio by deposition processes and sputter etching processes, which are alternately and repeatedly performed. However, conventional high-density plasma CVD processes also have certain limitations.
For instance, a conventional high-density plasma CVD process taught in U.S. patent Publication Ser. No. U.S. 2001/0019903 A1 to Shufflebotham et al., entitled “Inductively coupled plasma CVD”. According to Shufflebotham et al., conductive lines, which are adjacent to each other, are formed on a semiconductor substrate, and the semiconductor substrate having the conductive lines is loaded on a chuck installed inside a process chamber. A reactant gas such as a hydrogen gas, an oxygen gas, a nitrogen gas, an ammonia (NH3) gas or a nitrogen trifluoride (NF3) gas as well as a silicon-containing gas such as a silane (SiH4) gas, a silicon tetrafluoride (SiF4) gas, a disilane (Si2H6) gas or the like are then injected into the process chamber to form a material layer that fills gap regions between the conductive lines. Before forming the material layer, the chuck maintains a temperature of 80° C. to 200° C. to produce a material layer having low stress.
However, in the disclosure of Shufflebotham et al., the material layer may contain fluorine atoms because the fluorine atoms dissociate from fluorine-based gases, such as a SiF4 gas or a NF3 gas, and cannot be completely exhausted through the outlet of the process chamber. In addition, if a hydrogen gas is used as a reactant gas, hydrogen atoms in the hydrogen gas react with the fluorine atoms to produce hydrofluoric acid (HF). Further, since the process maintains a temperature at 200° C. or below, the hydrofluoric acid is not vaporized and remains in the process chamber. Thus, even though the hydrogen gas is used as a reactant gas, the fluorine atoms still remain in the material layer. The fluorine atoms contained in the material layer generate lung-shaped defects. Further, the hydrogen atoms in the hydrogen gas can also exist in the material layer. The hydrogen atoms present in the material layer generate bubble defects in the material layer during subsequent thermal processes.
Furthermore, the process chamber is made of an aluminum oxide (Al2O3). The fluorine atoms dissociated from the fluorine-based gas react with the aluminum oxide and corrode the process chamber during formation of the material layer. Thus, the semiconductor substrate in the process chamber is contaminated with aluminum atoms. In addition, when a nitrogen gas or a nitrogen-base gas is used as a reactant gas, nitrogen atoms in the reactant gas react with the material layer. For instance, the nitrogen atoms react with a silicon oxide layer to form a silicon oxynitride layer or a silicon nitride layer in the material layer. Therefore, the material layer may locally exhibit non-uniform etch rates. Further, if contact holes are to be etched in the material layer, the contact holes may have an abnormal profile or may not be completely open because the material layer exhibits non-uniform etch rates.
Furthermore, Japanese Patent Publication Nos. 10092816 A and 10229081 A discloses a process of forming a silicon oxide layer having a low dielectric constant (e.g., a fluorine-doped silicon oxide layer) on a semiconductor substrate. The fluorine-doped silicon oxide layer is formed using a SiF4 gas, and the semiconductor substrate is maintained at a temperature of below 400° C. so that the silicon oxide layer contains fluorine atoms dissociated from the SiF4 gas.
Therefore, a need exists for using a high-density plasma chemical vapor deposition process to form a material layer without fluorine atoms in gap regions in semiconductor devices to prevent the formation of defects in the semiconductor devices.